1. Field of the Invention
The present invention relates generally to a 1:n protection switching architecture for common processing units wherein 1 common processing unit protects n working common processing units.
As data becomes increasingly packet-oriented, there is an increased requirement to process the PCM (Pulse Modulation Transfer Mode) payload data. Examples of this processing include ATM (Asynchronous Transfer Mode) adaptation, DS0 (Digital Signal Level 0) to IP (Internet Protocol) telephony, and IP over ATM. In each of these examples, it is most cost effective to be able to increase the number of common processing units based upon the number of tributary interface units (and their bandwidth). As a result, typically there will be more than one on-line common processing unit.
Star bus related architectures allow the highest internal system bandwidth, but make increasing the number of common processing units more difficult, and especially make 1:n protection of the common processing units more difficult. The present invention resolves both of these problems by allowing 1:n protection wherein additional common processing use slots capable of accommodating either common processing units or tributary interface units.
In typical telecommunications systems, common processing units are usually protected by a 1:1 protection scheme wherein each working processing unit has one protection processing unit. Some systems, however, have multiple working common processing units of the same type. For example, if the common processing units in a switch or multiplexer system process a portion of the system payload traffic, it is advantageous to have multiple working common processing units. This approach reduces the amount of circuitry on each of the common processing units in order to reduce the cost of low bandwidth applications (which are typical at initial deployment) while providing a modular approach to increase the processing capability by adding more common processing units as the payload bandwidth increases. For example, one more working common processing unit could be added for every 14 DS1 (Digital Signal Level 1) interfaces.
Common processing units which handle the PCM payload include higher-speed interfaces (with multiplexing capability) and payload data processing units which perform format conversions (e.g., TDM (Time Division Multiplexing) to ATM conversion or TDM to IP packet conversion) or switching/routing. These types of common processing units are typically connected to the tributary interface units by either a bus or star related arrangement. The present invention is particularly advantageous for star-related PCM architectures since these architectures allow a much higher system data throughput than shared bus architectures.
2. Discussion of the Prior Art
Systems wherein common processing units share common buses with tributary units instead of a star connection and various 1:1 protected systems are disclosed by U.S. Pat. Nos. 5,408,462; 5,623,532; 4,477,895and 5,731,887.
Accordingly, it is a primary object of the present invention to provide a 1:n protection switching architecture for common processing units wherein 1 protection common processing unit protects n working common processing units.
Common processing units in multiplexer and switching systems typically have one dedicated protection (standby) common processing unit for each working common processing unit. In contrast thereto, the present invention provides a mechanism to allow a single protection common processing unit to provide protection for multiple working processor units. This type of protection is known as 1:n protection (i.e., 1 protection unit protects n working units). Common processing units can include payload data conversion units, high-speed interface units, or switch/routing units.
The present invention is particularly useful in systems wherein tributary interface units are connected to common processing units by a star related configuration in which the common processing unit (or unit pair) has a plurality of separate connections to the tributary interface units. The present invention allows common processing units to be located in either dedicated slots or in slots which can also be used by tributary interface units, while still providing 1:n protection regardless of where the common processing unit is located.
The present invention provides:
1) 1:n protection of common processing units (which are traditionally 1:1 protected);
2) a combined 1:1 and 1:n arrangement to allow additional, protected common processing units to be added to a star related architecture centered around another common processing unit;
3) 1:n protection for common processing units when there are more than two common processing units in a system, which lowers overall system costs;
4) a way to implement a star related connection architecture to common processor units while allowing the addition of more of that type of common processor unit to the legs of the star rather than at the center with protection, to increase system reliability.
The present invention provides:
(1) Lower initial system cost by allowing the number of common processing units to scale with system bandwidth and processing requirements,
(2) Lower overall system costs by allowing 1:n protection of common processing units rather than the traditional 1:1 protection, and
(3) Fast protection switching by a dedicated, high-speed download port from the system controller to the protection unit.
The present invention is ideally suited for a service access multiplexer or packet switch system or cell switch system which can perform protocol processing on payload data.
The present invention should greatly increase the marketability of service access multiplexer or packet or cell switch systems by allowing modular growth for low initial cost and by reducing the cost of a fully-loaded system by reducing the number of dedicated protection units.
The present invention allows modular growth of systems employing common processing units, which is especially important for systems handling packet or ATM data, and allows cost-effective 1:n protection of the common processing units with a star bus architecture providing a high internal system bandwidth.